Trying to understand the moveto_d BIOS sub

[jfmateos]

This is the code of the moveto_d BIOS sub

;-----------------------------------------------------------------------;
;       F312    Moveto_d                                                ;
;                                                                       ;
; This routine uses the current scale factor, and moves the pen to the  ;
; (y,x) position specified in D register.                               ;
;                                                                       ;
; ENTRY DP = $D0                                                        ;
;       A-reg = Y coordinate                                            ;
;       B-reg = X coordinate                                            ;
;                                                                       ;
;       D-reg trashed                                                   ;
;-----------------------------------------------------------------------;

Moveto_d:       STA     <VIA_port_a     ;Store Y in D/A register
               CLR     <VIA_port_b     ;Enable mux
               PSHS    D               ;Save D-register on stack
LF318:          LDA     #$CE            ;Blank low, zero high?
               STA     <VIA_cntl
               CLR     <VIA_shift_reg  ;Clear shift regigster
               INC     <VIA_port_b     ;Disable mux
               STB     <VIA_port_a     ;Store X in D/A register
               CLR     <VIA_t1_cnt_hi  ;timer 1 count high
               PULS    D               ;Get back D-reg
               JSR     Abs_a_b
               STB     -1,S
               ORA     -1,S
               LDB     #$40
               CMPA    #$40
               BLS     LF345
               CMPA    #$64
               BLS     LF33B
               LDA     #$08
               BRA     LF33D

LF33B:          LDA     #$04            ;Wait for timer 1
LF33D:          BITB    <VIA_int_flags
               BEQ     LF33D
LF341:          DECA                    ;Delay a moment
               BNE     LF341
               RTS

LF345:          BITB    <VIA_int_flags  ;Wait for timer 1
               BEQ     LF345
               RTS
But i cannot understand the purpose of this section

               PULS    D               ;Get back D-reg
               JSR     Abs_a_b
               STB     -1,S
               ORA     -1,S
               LDB     #$40
               CMPA    #$40
               BLS     LF345
               CMPA    #$64
               BLS     LF33B
               LDA     #$08
               BRA     LF33D

LF33B:          LDA     #$04            ;Wait for timer 1
LF33D:          BITB    <VIA_int_flags
               BEQ     LF33D
LF341:          DECA                    ;Delay a moment
               BNE     LF341
               RTS

LF345:          BITB    <VIA_int_flags  ;Wait for timer 1
               BEQ     LF345
               RTS
Could anyone explain it?
Thanks

[kokovec]

There's a pretty good explanation here:

www.playvectrex.com/designit/chrissalo/vectordisplay.htm

[jfmateos]

Thanks kokovec... it is very well explained but about the interesting part he says:

The next lines are IMHO not neccessary, all this computing of some extra cycles to wait. And actually I don't understand it. Since the additional waiting is done AFTER the timer reaches zero, that means the ~RAMP is disabled anyway, so no change to any vector position will occur.

I think these delays are important... but my assembler is not good enough to understand this part:


PULS    D               ;Get back D-reg
               JSR     Abs_a_b
               STB     -1,S
               ORA     -1,S

[kokovec]

I believe that code is in there for the calibration routines which isn't needed when drawing sprites.

[jfmateos]

Which callibration routines?

[kokovec]

I did some research on this a while back while I was designing an driver circuit for the Vectrex CRT.
From what I recall the the code hops around allot during initialization and calibration routines like Wait_Recal and Recalibrate.
It's not straight forward and I ended up using a logic probe to figure out routine calls and integration timing.

[jfmateos]

This is very interesting kokovec, as I am working in the Vectrex2TV project.